晶体振荡器布线设计指导

晶体振荡器布线设计指导

Oscillator Printed Circuit Board (PCB) Design Guidelines晶体振荡器布线设计指导

晶体振荡器布线设计指导 Layout the oscillator footprint on the PCB as close as possible to the input pins of the chip.
把晶体振荡器连接到芯片的输入引脚,距离越近越好。

晶体振荡器布线设计指导The length of traces should be as short as possible and must not cross other signal lines.
走线应尽可能短,不得跨越其他信号线。

晶体振荡器布线设计指导Avoid right angle bends on traces. Capacitance increases in the 45° corner region changing the characteristic impedance of the trace, leading to reflections. This can be mitigated by rounding right angles.
避免时钟信号走线中出现直角。在电路中45°角区域容易造成电容增加,这将改变走线阻抗特性,导致反射干扰信号。建议通过走弯角方式来减轻反射。

晶体振荡器布线设计指导A good practice is to have the oscillator connected to the common ground plane.
将振荡器连接到公共接地平面。

晶体振荡器布线设计指导Do not lay out the ground (GND) pattern under oscillator, this adds parasitic capacitance.
不要在晶体振荡器下方走接地线(GND),以免增加寄生电容。

晶体振荡器布线设计指导Do not run Digital / RF signal lines or power under oscillators for multi-layered PCB, as this will add noise.
不要在多层PCB的振荡器下布置数字线/射频信号线或电源线,以免增加噪声。

晶体振荡器布线设计指导To ensure optimal oscillator performance, place a by-pass capacitor of 0.1uF as close to the part as possible between Vdd and GND pads.

为了确保振荡器最佳性能,请增加一颗0.1 uF 旁路电容,并将其尽可能靠近 Vdd 和 GND 焊盘之间的部分。0.1 uF 旁路电容的作用是降低来自电源杂波对晶体振荡器的负面影响。

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